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december 2006 rev 3 1/62 62 STE2007 96 x 68 single-chip lcd controller/driver features 68 x 96 bits display data ram 33,49, 65 and 68 lines mode row by row scrolling interfaces ? 3-lines serial interface (read and write) ?i 2 c (read and write) ? 4-line serial (read and write) partial display mode (33,25,17,9 lines mode) fully integrated oscillator that requires no external components cmos compatible inputs programmable id-number programmable bias ratio programmable columns organization fully integrated configurable lcd bias voltage generator with: ? selectable multiplication factor (3x, 4x and 5x) ? effective sensing for high precision output ? eight selectable temperature compensation coefficients designed for chip-on-glass (cog) applications low power consumption, suitable for battery operated systems interfaces supply voltage range from 1.6 to 3.6v high voltage generator supply voltage range from 2.4 to 3.6v display supply voltage range from 3 to 13.2v description the STE2007 is a low power lcd driver, capable to drive 96 columns and up to 68 lines, designed for monochrome displays. the STE2007 includes fully integrated bias voltage generator (up to 5x multiplication factor), and internal oscillator, thus reducing to minimum the number of external components required and the current consumption. the STE2007 features the three standard serial interfaces (3 and 4 lines serial, i 2 c interface). www.st.com
content STE2007 2/62 content 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 driver pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 cpu interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 test pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 display driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 mcu tx data mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 driver txdata mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 3-lines 9 bit serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.1 mcu txdata mode (write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 driver txdata mode (read mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 4-line spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.1 mcu txdata mode (write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 driver txdata mode (read mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.1 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.2 starting the communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.3 mcu txdata mode (write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.4 driver txdata mode (read mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 reading mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.1 iidentification byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 display data ram (ddram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 ddram and page/column address circuit . . . . . . . . . . . . . . . . . . . . . . . . 27
STE2007 content 3/62 5.2 line address circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 partial display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.1 33 line partial display mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.2 25 line partial display mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.3 17 line partial display mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.4 9 line partial display mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.4 command parameters default configuration . . . . . . . . . . . . . . . . . . . . . . 38 6 instruction setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1 initialization (power on sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2 display data writing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 power on/power off timing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 display on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2 display normal/reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3 display all points on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4 page address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.5 column address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.6 display start line address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.7 segment driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.8 common driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.9 display data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.10 data reading from driver (driver txdata?mode) . . . . . . . . . . . . . . . . . . . 46 8.11 power control set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.12 vlcd set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.12.1 v0r - voltage range set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.12.2 vop set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.12.3 electronic volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.13 power saver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.14 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.15 nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.16 image location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
content STE2007 4/62 8.17 bias ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.18 temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.19 charge pump multiplication factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.20 refresh rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.21 icon mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.22 n- line inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.23 number of lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9 chip mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
STE2007 introduction 5/62 1 introduction in this document is specified lcd driver for black&white full graphic displays with a resolution of 96x68, 96x65, 96x49, and 96x33 (columnsxrows). abbreviations lcd liquid crystal display cog chip on glass ?technology mcu micro controller unit ddram display data random access memory msb most significant bit lsb least significant bit t.b.d. to be defined table 1. general driver parameters driver assembly technology chip on glass (cog) memory size (columns x rows) 96x68 ddram capacity: 6528 bits mux 1:68 1:65 1:49 1:33 frame frequency (hz) 65 70 75 80
introduction STE2007 6/62 figure 1. chip mechanical drawing STE2007 (0,0) x y bump side ! / ! ! 72 m 45 m r65 vss_aux vss_aux vss_aux vss_aux r67 r66
STE2007 driver pin description 7/62 2 driver pin description 2.1 cpu interface pins 2.2 power supply pins table 2. cpu interface logic signal type description note !res i reset input !cs i chip select input when low the communication port is enabled sdout 0 serial data output must be connected to sdain at module level sdain i serial data input /i 2 c interface data input sclk i serial clock input/i 2 c interface clock sda_out 0 i 2 c bus data out must be left floating when i 2 c interface is not is use sa1 i i 2 c slave address cannot be left floating sa0 i i 2 c slave address cannot be left floating !d/c i 4 line spi data/command selector must be connected to vssaux at module level when 4-line spi is not in use table 3. power supply pins signal type description note vss power analog & digital grounds vss_lcd power drivers analog ground vss_cp power booster ground vddi power digital power vdd power analog supply vdd_cp power booster power supply vssaux power auxiliar vss output
driver pin description STE2007 8/62 2.3 configuration pins table 4. high voltage pins signal type description note v lcd high voltage booster output cext = 0.1-1 f connected to vss v lcd_sense high voltage booster sense input must be connected to vlcd at module level com0 to com67 high voltage lcd row driver output unused lines must be left floating coms high voltage lcd row driver output unused lines must be left floating seg0 to seg95 high voltage lcd column driver output unused lines must be left floating table 5. configuration pin description signal type config description note oscin i vss/vssaux internal oscillator stopped vddi internal oscillator active sel0 -sel1 i ida i vss/vssaux ida=?0? vddi ida=?1? idb i vss/vssaux idb=?0? vddi idb=?1? sel1 sel0 interf a vss/vssaux vss//vssaux i 2 c vss/vssaux vdd1 spi 4-lin e vdd1 vss/vssaux serial 3-li n vdd1 vdd1 not u s
STE2007 driver pin description 9/62 2.4 test pins table 6. test pin description signal type description note t2 i test input. enable test mode. must be connected to vss in normal working mode t1 i test input. enable test mode. must be connected to vss in normal working mode t0 i test input. must be connected to vss in normal working mode t3 o test output. must be open in normal working mode t4 o test output. must be open in normal working mode t5 o test output. must be open in normal working mode t6 o test output. must be open in normal working mode vref_buff o analog test output must be left floating
electrical characteristics STE2007 10/62 3 electrical characteristics 3.1 absolute maximum ratings note: (*) esd tests have been performed with vss, vss_lcd and vss_cp shorted together table 7. absolute maximum ratings symbol parameter value unit v ddi supply voltage range - 0.5 to + 5 v v dd supply voltage range - 0.5 to + 5 v v lcd lcd supply voltage range - 0.5 to + 14.0 v i ss supply current - 50 to +50 ma v i digital inputs voltage -0.5 to v ddi + 0.5 v i in dc input current - 10 to + 10 ma i out dc output current - 10 to + 10 ma p tot total power dissipation (t j = 85c) 300 mw p o power dissipation per output 30 mw t j operating junction temperature (1) 1. device behavior and characterization are measur ed over this temperatur e range during internal qualification of the product. during production testing, however, device performance is measured at a fixed ambient temperature, typically 25c. -25 to + 85 c t stg storage temperature - 65 to 150 c vdd pin vs vddi (*) esd maximum withstanding voltage range test condition : cdf-aec-q100-002-"human body model" acceptance criteria: "normal performance 1500 v all pins (2) vs vddi 2. except vdd pin 1750 v all pins vs power supplies (3) 3. except vddi supply 2000 v
STE2007 electrical characteristics 11/62 3.2 dc characteristics vdd1 = 1.7 to 3.6 v; vdd2 = 1.75 to 4.2v; vss1,2 = 0v; vlcd = 4.5 to 14.5 v; tamb = 25c; unless otherwise specified. table 8. dc characteristics symbol parameter test condition min. typ. max. unit v dd, v ddcp power supply voltage operating voltage 2.4 3.6 v v ddi power supply voltage(logic) i/o supply voltage 1.6 3.6 v v lcd booster output 13.5 v v lcd_sense booster sense input 13.5 v v lcd lcd supply voltage accuracy v lcd =10v; vdd=2.6v; no display load; f sclk =0hz -2.2 2.2 % i(v ddi ) logic supply current power saver mode on (interfaces quiescent) 15 a power saver mode off (interfaces quiescent) 620 a write mode 120 250 a i(v dd +v ddcp ) analog supply current v lcd =10v;booster= 5x; f sclk =0hz; vdd=2.4v refresh rate=75hz; no display load 90 180 a logic inputs v ih logic high level input voltage 0.7v ddi v ddi v v il logic low level input voltage vss 0.3v ddi v i ih logic high level input current 1 a i ll logic low level input current -1 a logic outputs v oh logic high level output voltage l out = -500 a; vddi=1.6v 0.8v ddi v ddi v v ol logic low level output voltage l out = 500 a; vddi=1.6v vss 0.2v ddl v
electrical characteristics STE2007 12/62 3.3 ac characteristics tamb = 25c; unless otherwise specified. 3.4 mcu tx data mode note: 1 the input signal rise and fall times must be within 10ns. 2 every timing is specified on the basis of 30% and 70% of vddi. figure 2. mcu txdata timing table 9. ac operation - internal oscillator symbol parameter test condition min. typ. max. unit f frame frame frequency default vddi= 1.6; vdd= 2.9v rafresh rate = 75hz 65 75 84 hz table 10. ac characteristics for serial interface symbol signal description notes min. typ. max. unit tcss !cs chip select 60 ns tcsh 100 ns tchw 50 ns tsds sdain input serial data interface data setup time 100 ns tsdh data hold time 100 125 ns tac sdaout output serial data interface access time 0 100 ns tod output disable time 25 100 ns tscyc sclk serial clock input serial clock cycle 250 ns tshw serial clock h pulse width 100 ns tslw serial clock l pulse width 100 ns !cs sclk sda/mcu txdata tcss tcsh tscyc tslw tshw tr tsdh tsds tf tchw tchw
STE2007 electrical characteristics 13/62 3.5 driver txdata mode note: 1 data hold time t1 depends on sclk high time and max data hold time. it is always 3-8ns before sclk pulse falling edge 2 the input signal rise and fall times must be within 10ns. 3 every timing is specified on the basis of 30% and 70% of vddi. note: 1 the input signal rise and fall times must be within 10ns. 2 every timing is specified on the basis of 30% and 70% of vddi. table 11. input signals change time signal symbol parameter min. typ. max. unit inputs tr,tf (1) 1. to 30% & 70% levels 10 ns table 12. timings based on 4 mhz sclk speed symbol item condition min. typ. max. units t1 data hold time note 1 100 125 ns t2 access time ? 10 100 ns t3 output disable time ? 25 100 ns t4 data setup time ? 100 ? ns t5 !cs pulse width high ? 250 ns table 13. timings based on 1 mhz sclk speed symbol item condition min. typ. max. units t1 data hold time ? 100 125 ns t2 access time ? 10 450 ns t3 output disable time ? 25 450 ns t4 data setup time ? 100 ? ns t5 1cs pulse width high ? 250 ns
electrical characteristics STE2007 14/62 figure 3. driver txdata mode ac timing characteristics 3.5.1 reset timing note: 1 the input signal rise and fall times must be within 10ns. 2 every timing is specified on the basis of 30% and 70% of vddi. hiz status t1 t2 t3 t4 tx tx rx command command hiz sclk hiz hiz timing b timing a timing a timing b !cs !cs mcu txdata driver txdata sclk sclk driver txdata mcu txdata mcu data direction driver txdata mcu txdata driver sda direction in out out in driver sda direction t5 d/c 1/2 sclk 1/2 sclk table 14. reset timing symbol signal description min. max. unit trs !res reset time 2500 ns trw !res reset low pulse width (for valid reset) 2500 trj !res reset rejection (for noise spike) 1000
STE2007 electrical characteristics 15/62 figure 4. reset timing trs !res trw during reset normal operation internal circuit status trj
interface STE2007 16/62 4 interface 4.1 3-lines 9-bit serial interface STE2007 3-lines 9 bits serial interface is a bidirectional link between the display driver and the host processor. it consists of three lines: ? sdain/sdaout serial data ? sclk serial clock ? !cs peripheral enable: - active low- enables and disables the serial interface the serial interface is active only if the !cs line is low. if !cs is low after the positive edge of !res, the serial interface is ready to receive data after the internal reset time. serial data must be input to sda in the sequence d/!c, d7 to d0. STE2007 read data on sclk rising edge. the first bit of serial data d/!c is data/command flag. when d/!c =?1? d7 to d0 bits are display ram data or command parameters. when d/!c=?0? d7 to d0 bits identify a command 4.1.1 mcu txdata mo de (write mode) STE2007 is always a slave device on the communication bus and receive the communication clock on the sclk pin from the master. information are exchanged word- wide. every word is composed by 9 bit. the first bit is named d/!c and indicates whether the following byte is a command (d/!c =0) or a display data byte (d/!c =1). during data transfer, the data line is sampled by the receiver unit on the sclk rising edge. the data/command received is transferred to ddram or executed on the first falling edge after the latching rising edge or on the !cs rising edge. if !cs stays low after the last bit of a command/data byte, the serial interface expects the d/!c bit of the next data byte on the next sclk positive edge. a reset pulse on !res pin interrupts any transmission. figure 5. mcu txdata mode 4.1.1.1 data/command transfer break if the host processor generates an break condition (!cs line high before having received bit d0) while transferring a data byte to the frame memory or a command identifier or a command parameter, the not complete received byte is discarded, the communication is interrupted and the interface is forced in reset state. when !cs line becomes low again to start a new communication session STE2007 is ready to receive the same byte interrupted re-transmitted or a new command identifier. !cs d/c d7 d6 d5 d4 d3 d2 d1 d0 d/c 123456789 sclk d7 d6 d5 d4 11 10 12 13 14 sda
STE2007 interface 17/62 figure 6. 3-lines spi data transfer break condition 4.1.1.2 data/command transfer pause it is possible while transferring frame memory data, commands or command parameters to insert a pause in the data transmission (!cs line high after 8 bits received). when !cs is forced high after a whole byte received, the received byte is processed. then STE2007 is forced in a wait state ready to restart processing incoming data from the point where the communication has been paused if a new command identifier is transferred after a pause condition the previous communication session is definitively closed. four are the possible conditions: ? command-pause-command ? command-pause-parameter ? parameter-pause-command ? parameter-pause-parameter figure 7. 3-lines spi data transfer pause lr0204 d7 d6 d5 d4 d3 d7 d6 d5 d4 !cs sda scl command/parameter command/parameter break d/!c lr020 3 d3 d2 d1 d0 d7 d6 d5 d4 d3 !cs sda scl command/parameter command/parameter pause d2 d1 d0 d/!c
interface STE2007 18/62 4.1.2 driver txdata mode (read mode) the driver txdata?mode is a method to check the electrical interconnection between lcd driver and baseband, to identify the driver and for vdd intercfonnection electrical self testing. self testing of the electrical contacts is based on the monitoring of vlcd. the improper electrical contact on vdd can be noted from a too low level of vlcd. the serial interface driver txdata?mode is controlled by three input signals. the serial data output (sdaout/driver txdata) and serial clock input (sclk) are enabled when !cs is low after having received one reading command. to access driver txdata?mode a reading command must be sent to STE2007 driver. the first bit (d/c) is low to indicates next 8?bits are for command. the data is read to the driver on the rising edge of sclk (see section ?mcu txdata?mode?). after last command bit (bit 0) is read sdaout becomes active (low impedance) and mcu is able to read data from driver. sdaout is forced in high impedence when !cs line is forced high or after the eight sclk rising edges from the last sclk rising edge of teh reading command transfer (figure 8). after sending out all 8 bits the driver release automatically the bus and go back to the mcu txdata?mode. mcu txdata line changes from high?z to active low or high in the falling edge of 8th sclk pulse. !cs must be set high and low again before !d/c writing can continue. if !cs is forced high during the driver txdata-mode, the driver tx data session is aborted and sdaout is forced in high impedance mode. sdaout and sdain line can be short circuited in normal working conditions.
STE2007 interface 19/62 figure 8. ac timing characteristics figure 9. timing chart for start and stop of data reading from driver hiz status t1 t2 t3 t4 tx tx rx command command hiz sclk hiz hiz timing b timing a timing a timing b !cs !cs mcu txdata driver txdata sclk sclk driver txdata mcu txdata mcu data direction driver txdata mcu txdata driver sda direction in out out in driver sda direction t5 d/c 1/2 sclk 1/2 sclk driver txdata mcu txdata d/c='0' 7 1 sclk 1 0 !cs ... ... ... ... ... ... 7 mcu txdata begins driver txdata begins ... 6 high z 1 289 1 2 7 8 2 1 d/c 7 self test command writing reading of status d/c writing 0 mcu txdata begins 0 high z
interface STE2007 20/62 4.2 4-line spi STE2007 4-lines serial interface is a bidirectional link between the display driver and the host processor. it consists of four lines: ?sda serial data ? scl serial clock ? !cs peripheral enable: - active low- enables and disables the serial interface ? mode selection (d/!c). the serial interface is active only if the !cs line is low. if !cs is low after the positive edge of !res, the serial interface is ready to receive data after the internal reset time. 4.2.1 mcu txdata mo de (write mode) STE2007 is always a slave device on the communication bus and receive the communication clock on the scl pin from the master. information are exchanged byte-wide. during data transfer, the data line is sampled by the receiver unit on the scl rising edge. d/!c line status set whether the byte is a command (d/!c =0) or a data (d/!c =1); d/!c line is read on the eighth scl clock pulse during every byte transfer. if !cs stays low after the last bit of a command/data byte, the serial interface expects the msb of the next data byte on the next scl positive edge. if !cs line is forced high in the middle of a data transfer, not complete data bytes and commands bytes are discarded. a reset pulse on !res pin interrupts any transmission. figure 10. 4-lines spi commands transfe figure 11. 4-lines spi video data write cycle d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 lr018 9 hi-z d6 d5 d4 d3 d2 d1 d0 d7 d6 command command command command d0 d7 d6 d5 d4 d3 d2 d1 d0 d/!c !cs sda (input) scl sda (output) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 lr019 0 hi-z d6 d5 d4 d3 d2 d1 d0 d7 d6 command data to video ram d0 d7 d6 d5 d4 d3 d2 d1 d0 d/!c !cs sda (input) scl sda (output) data to video ram data to video ram
STE2007 interface 21/62 4.2.1.1 data/command transfer break if the host processor generates an break condition (!cs line high before having received bit d0) while transferring a data byte to the frame memory or a command identifier or a command parameter, the not complete received byte is discarded, the communication is interrupted and the interface is forced in reset state. when !cs line becomes low again to start a new communication session STE2007 is ready to receive the same byte interrupted re-transmitted or a new command identifier. figure 12. 4-lines spi data transfer break condition 4.2.1.2 data/command transfer pause it is possible while transferring frame memory data, commands or command parameters to insert a pause in the data transmission (!cs line high after 8 bits received). when !cs is forced high after a whole byte received, the received byte is processed. then STE2007 is forced in a wait state ready to restart processing incoming data from the point where the communication has been paused if a new command identifier is transferred after a pause condition the previous communication session is definitively closed. four are the possible conditions: ? command-pause-command ? command-pause-parameter ? parameter-pause-command ? parameter-pause-parameter d7 d6 d5 d4 d3 d7 d6 d5 d4 d3 d/!c !cs sda scl lr019 2 command/parameter command/parameter break
interface STE2007 22/62 figure 13. 4-lines spi data transfer pause 4.2.2 driver txdata mode (read mode) throughout sda line is possible to read some registers value (id numbers, status byte, temperature). sda (output driver) is in high impedance in steady state and during data write. figure 14. 4-lines spi 8-bit read cycle 4.3 i 2 c bus the i 2 c interface is a fully complying i2c bus specification, selectable to work in both fast (400khz clock) and high speed mode (3.4mhz). this bus is intended for communication between different ics. it consists of two lines: one bi-directional for data signals (sda) and one for clock signals (scl). both the sda and scl lines must be connected to a positive supply voltage via an active or passive pull-up. the following protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop data transfer condition (see below). accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. lr0191 d3 d2 d1 d0 d7 d6 d5 d4 d3 d/!c !cs sda scl command/parameter command/parameter pause d2 d1 d0 lr025 5 !cs scl read command data sda (input) d7 d6 d5 d4 d3 d2 d1 d0 d0 d7 d6 d5 d4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 sda (output) high z high z mcu data tx start mcu data tx start lcd driver data tx start next command d!c
STE2007 interface 23/62 start data transfer: a change in the state of the data line, from high to low, while the clock is high, define the start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock signal is high, defines the stop condition. data valid: the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer starts with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and the stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with the ninth bit. by definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". the device that controls the message is called "master". the devices that are controlled by the master are called "slaves" acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda_in line during the acknowledge clock pulse. of course, setup and hold time must be taken into account. a master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave the data line high to enable the master to generate the stop condition. connecting sda_in and sda_out together the sda line become the standard data line. having the acknowledge output (sdaout) separated from the serial data line is advantageous in chip-on-glass (cog) applications. in cog applications where the track resistance from the sdaout pad to the system sda line can be significant, a potential divider is generated by the bus pull-up resistor and the indium tin oxide (ito) track resistance. it is possible that during the acknowledge cycle the STE2007 will not be able to create a valid logic 0 level. by splitting the sda input from the output the device could be used in a mode that ignores the acknowledge bit. in cog applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the sdack pad to the system sda line to guarantee a valid low level. to be compliant with the i 2 c-bus hs-mode specification the STE2007 is able to detect the special sequence "s00001xxx". after this sequence no acknowledge pulse is generated. since no internal modification are applied to work in hs-mode, the device is able to work in hs-mode without detecting the master code.
interface STE2007 24/62 figure 15. bit transfer and start,stop conditions definition figure 16. acknowledgment on the i 2 c-bus 4.3.1 communication protocol the STE2007 is an i 2 c slave. the access to the device is bi-directional since data write and status read are allowed. four are the device addresses available for the device. all have in common the first 5 bits (01111). the two least significant bit of the slave address are set by connecting the sa0 and sa1 inputs to a logic 0 or to a logic 1. 4.3.2 starting the communication to start the communication between the bus master and the slave lcd driver, the master must initiate a start condition. following this, the master sends an 8-bit byte, on the sda bus line (most significant bit first). this consists of the 7-bit device address code, and the 1- bit read/write designator (r/w ). the r/w bit has to be set to logic 1 to logic 0 according to the type of communication (read or write). all slaves with the corresponding address acknowledge in parallel, all the others ignore the i 2 c-bus transfer. figure 17. addree byte data line stable data valid change of data allowed start condition stop condition clock data d00in1151 start clock pulse for acknowledgement data output by receiver sclk from master data output by transmitter d00in1152 1 msb lsb 289 STE2007 slave address s 01111 0 a r / w s 1 a read or write designator address byte
STE2007 interface 25/62 4.3.3 mcu txdata m ode (write mode) if the r/w bit is set to logic 0 the STE2007 is set to be a receiver and the master can send commands or data. after the communication has started and slaves have acknowledged, the master sends a control byte defined as follows and waits for its acknowledgement: the co bit is the control byte msb and defines if after this control byte will follow a single byte sequence (co = 1) or a multiple bytes sequence (co = 0). the d/c bit defines whether the following byte (if co = 1) or the following stream of bytes (if co = 0) are command (d/c = 0) or ddram data (d/c = 1). depending on state of flags co and d/c, four writing sequences are possible: single command byte sequence (co = 1, d/c = 0): a single byte interpreted as a command will follow the control byte; single data byte sequence (co = 1, d/c = 1): a single byte interpreted as a data to be written in ddram will follow the control byte; multiple command bytes sequence (co = 0, d/c = 0): a stream of bytes will follow the control byte, with each single byte interpreted as a command; multiple data bytes sequence (co = 0, d/c = 1): a stream of bytes will follow the control byte, with each byte interpreted as a data byte to be written in ddram. every single byte of a sequence must be acknowledged by all addressed units. a multiple data sequence is terminated only by sending a stop condition on the i 2 c bus. when a sequence is terminated, another sequence of any type can follow or a i 2 c stop condition can be sent to close the communication. in a single or multiple data bytes sequence, every data byte received is stored in the ddram at the location specified by the current values of data pointers. data pointers are automatically updated after each single data byte written. control byte co dc 000 000
interface STE2007 26/62 4.3.4 driver txdata mode (read mode) if the r/w bit is set to logic 1 the chip will output data immediately after the slave address. if the d/c bit during the last write access, is set to a logic 0, the byte read is the status byte. figure 18. communication protocol lr0008d master ack communication start i2c start cond 0 111 1 0 a STE2007 ack r/w slave address sa1 co a control byte command byte a STE2007 ack STE2007 ack command byte d/c 000 10 single command sequence co a control byte command byte a STE2007 ack STE2007 ack first command byte d/c 000 00 multiple command sequence command byte a STE2007 ack last command byte co a control byte STE2007 ack d/c 000 11 single data sequence multiple data sequence data byte a data byte STE2007 ack co a control byte data byte a STE2007 ack STE2007 ack first data byte d/c 000 01 data byte a STE2007 ack last data byte communication stop i2c stop cond status byte read sequence i2c start cond 01111 0a STE2007 ack r/w slave address a i2c start cond status byte read mode write mode sa2 000 000 000 000 sa1 sa2
STE2007 interface 27/62 4.4 reading mode STE2007 features a reading command to transmitt data from the lcd driver to host processor. after the reading command STE2007 transfers 8 bits to the host controller: ? identification byte (command code db hex ) 4.4.1 iidentification byte identification byte is an 8 bit code that identify the module revision number. figure 19. identification byte in reading mode figure 20. identification information table 15. id byte format bit nrd7(msb)d6d5d4d3d2d1d0(lsb) 00idb padida pad0000 asic(mcu) STE2007 sda sclk xcs power ic vdd vddi gnd reset vlcd voltage booster lcd power supply circuit driver txdata mcu txdata driver side baseband side auto return id multi plexer command decoder test 8 bit register vdd vddi vss vsscp vddcp send rading command (dbh) read status(id data) send reset command identification information command:e2h
display data ram (ddram) STE2007 28/62 5 display data ram (ddram) 5.1 ddram and page/column address circuit the ddram stores pixel data for lcd. it is a 68?row (8 page by 8 bits +4) by 96?column addressable array. d7 to d0 display data from mcu corresponds to the lcd common direction. ?0? bit in ddram is a off?dot on display and ?1? bit in ddram is displayed as on?dot on display. figure 21. ddram vs. display on lcd each pixel can be selected when page address and column address are specified. the mcu issues page address set command to change the page and access to another page. in ddram page address 8 (d3,d2,d1,d0=1,0,0,0) only display data d0,d1,d2 & d3 are valid. the ddram column address is specified by column address set command. the specified column address is automatically incremented by +1 when a display data write command is entered. after the last column address (5fh), column address returns to 00h and page address incremented by +1. after the very last address (column=5fh, page=8h), both column address and page address return to 00h (column address=00h, page address=0h). figure 22. column address in normal mode 011 1 1 d0 com0 100 0 0 d1 com1 000 0 1 d2 com2 001 1 0 d3 com3 110 0 1 d4 com4 ddram display on lcd 0h 1h 2h 3h 4h 5h 0 1 2 94 95 96 97 98 192 193 194 288 289 290 384 385 386 480 481 482 190 191 286 287 382 383 478 479 574 575 00h 01h 02h 5eh 5fh d0 d1 d2 d3 d4 d5 d6 d7 data page address column address 6h 7h 8h 576 577 578 672 673 674 768 769 770 670 671 766 767 862 863 data for page address 0h to 07h d0 data for page address 8h lsbit msbit d1 d2 d3
STE2007 display data ram (ddram) 29/62 figure 23. column address in reversed mode data can be written to the ddram at the same time as data is being displayed, without causing the lcd to flicker. segment driver direction command can be used to reverse the relationship between the ddram column address and segment output. this function is achieved writing data into ddram in reverse order (from right to left). table 16. column address direction 5.2 line address circuit the line address circuit specifies the line address relating to the com output when the contents of the ddram are displayed. the display start line that is normally the top line of the display, can be specified by display start line address set command. STE2007 features four different multiplexing mode to fine tune the duty ratio on the display size: ? 68 lines display ? 65 lines display ? 49 lines display ? 33 lines display column address 00h 01h 02h 5dh 5eh 5fh 5dh normal direction seg0 seg1 seg2 _ _ _ _ _ _ seg93 seg94 seg95 reverse direction seg95 seg94 seg93 _ _ _ _ _ _ seg2 seg1 seg0 0h 1h 2h 3h 4h 5h 96 97 98 192 193 194 288 289 290 384 385 386 480 481 482 190 191 286 287 382 383 478 479 574 575 00h 01h 02h 5eh 5fh d0 d1 d2 d3 d4 d5 d6 d7 data page address column address 6h 7h 8h 576 577 578 672 673 674 768 769 770 670 671 766 767 862 863 data for page address 0h to 07h d0 data for page address 8h 95 94 lsbit msbit d1 d2 d3
display data ram (ddram) STE2007 30/62 figure 24. m68?line mode d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 column address 00h 01h 02h 06h 03h 04h 05h 59h 5ah 5bh 5fh 5ch 5dh 5eh 00h page address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh s e g 0 s e g 95 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 95 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 seg output normal direction reverse direction line address start d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 0 0 d0 com64 com64 page 8 d1 d2 d3 40h 41h 42h 43h com65 com66 com65 com66 coms coms com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com1 1 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 display start line does not access 65th, 66th, 67th, 68th line display start line does not access 65th, 66th, 67th, 68th line com64 com64 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 start 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh line address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 40h 41h 42h 43h com65 com66 coms com65 com66 coms iconmode="1" iconmode="0"
STE2007 display data ram (ddram) 31/62 figure 25. 65?line mode d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 column address 00h 01h 02h 06h 03h 04h 05h 59h 5ah 5bh 5fh 5ch 5dh 5eh 00h page address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh s e g 0 s e g 95 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 95 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 seg output normal direction reverse direction line address start d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 0 0 d0 com64 com64 page 8 d1 d2 d3 40h 41h 42h 43h com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 display start line does not access 65th, 66th, 67th, 68th line com64 com64 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 iconmode="1" iconmode="0" start 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh line address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 40h 41h 42h 43h
display data ram (ddram) STE2007 32/62 figure 26. 49?line mode d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 column address 00h 01h 02h 06h 03h 04h 05h 59h 5ah 5bh 5fh 5ch 5dh 5eh 00h page address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh s e g 0 s e g 95 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 95 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 seg output normal direction reverse direction line address start d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 0 0 d0 com64 com64 page 8 d1 d2 d3 40h 41h 42h 43h com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 display start line does not access 65th, 66th, 67th, 68th line iconmode="1" iconmode="0" start 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh line address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 40h 41h 42h 43h com48 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 com48
STE2007 display data ram (ddram) 33/62 figure 27. 33?line mode 5.3 partial display STE2007 feature four configuration for partial display function: ? 33 line partial display ? 25 line partial display ? 16 line partial display ? 9 line partial display partial display area location on the screen is defined by image location parameter. image location + partial display area > multiplexing rate. d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 column address 00h 01h 02h 06h 03h 04h 05h 59h 5ah 5bh 5fh 5ch 5dh 5eh 00h page address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh s e g 0 s e g 95 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 95 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 seg output normal direction reverse direction line address start d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 0 0 d0 com64 com64 page 8 d1 d2 d3 40h 41h 42h 43h com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 display start line does not access 65th, 66th, 67th, 68th line iconmode="1" iconmode="0" 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh line address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 40h 41h 42h 43h com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 normal direction reverse direction com output com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 start
display data ram (ddram) STE2007 34/62 figure 28. illustration of partial display when partial display mode is enabled the user has to update the operative voltage, bias ratio and charge pump setting to match the new working conditions. 5.3.1 33 line partial display mode partial display area is composed of 33 lines. memory vs. row drivers mapping is defined according to the following parameters: ? multiplexing value ? il[2:0] figure 29. example: partial display 33 lines & mux65 display display image location + partial display area width <= multiplexing rate image location + partial display area width > d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 column address 00h 01h 02h 06h 03h 04h 05h 59h 5ah 5bh 5fh 5ch 5dh 5eh 00h page address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh s e g 0 s e g 95 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 95 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 seg output normal direction reverse direction line address d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 0 0 d0 coms0 coms0 page 8 d1 d2 d3 40h 41h 42h 43h com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 display start line does not access 65th, 66th, 67th, 68th line coms0 coms0 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 iconmode="1" iconmode="0" 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh line address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 40h 41h 42h 43h start partial display area (32 +1) start partial display area (33) il[2:0] il[2:0]
STE2007 display data ram (ddram) 35/62 figure 30. example: partial display 33 lines & mux68 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 column address 00h 01h 02h 06h 03h 04h 05h 59h 5ah 5bh 5fh 5ch 5dh 5eh 00h page address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh s e g 0 s e g 95 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 95 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 seg output normal direction reverse direction line address d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 0 0 d0 page 8 d1 d2 d3 40h 41h 42h 43h display start line does not access 65th, 66th, 67th, 68th line iconmode="1" iconmode="0" 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh line address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 40h 41h 42h 43h start partial display area (32 +1) start partial display area (33) il[2:0] il[2:0] com64 com64 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 com65 com66 coms com65 com66 coms com64 com64 com65 com66 com65 com66 coms coms com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com1 1 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0
display data ram (ddram) STE2007 36/62 5.3.2 25 line partial display mode partial display area is composed of 25 lines. memory vs. row drivers mapping is defined according to the following parameters: ? multiplexing value ? il[2:0] figure 31. example: partial display 25 lines & mux65 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 column address 00h 01h 02h 06h 03h 04h 05h 59h 5ah 5bh 5fh 5ch 5dh 5eh 00h page address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh s e g 0 s e g 95 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 95 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 seg output normal direction reverse direction line address d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 0 0 d0 com64 com64 page 8 d1 d2 d3 40h 41h 42h 43h com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 display start line does not access 65th, 66th, 67th, 68th line com64 com64 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 iconmode="1" iconmode="0" 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh line address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 40h 41h 42h 43h start partial display area (24 +1) start partial display area (25) image location (il[2:0]) + partial display area width (19 hex ) <= multiplexing rate (40 hex ) il[2:0] il[2:0]
STE2007 display data ram (ddram) 37/62 5.3.3 17 line partial display mode partial display area is composed of 17 lines. memory vs. row drivers mapping is defined according to the following parameters: ? multiplexing value ? il[2:0] figure 32. partial display 17 lines d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 column address 00h 01h 02h 06h 03h 04h 05h 59h 5ah 5bh 5fh 5ch 5dh 5eh 00h page address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh s e g 0 s e g 95 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 95 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 seg output normal direction reverse direction line address d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 0 0 d0 com64 com64 page 8 d1 d2 d3 40h 41h 42h 43h com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 display start line does not access 65th, 66th, 67th, 68th line com64 com64 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 iconmode="1" iconmode="0" 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh line address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 40h 41h 42h 43h start partial display area (16+1) start partial display area (17) image location (1l[2:0]) + partial display area width (11 hex ) <= multiplexing rate (40 hex ) il[2:0] il[2:0]
display data ram (ddram) STE2007 38/62 5.3.4 9 line partial display mode partial display area is composed of 9 lines. memory vs. row drivers mapping is defined according to the following parameters: ? multiplexing value ? il[2:0] figure 33. partial display 9 lines d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 column address 00h 01h 02h 06h 03h 04h 05h 59h 5ah 5bh 5fh 5ch 5dh 5eh 00h page address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh s e g 0 s e g 95 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 95 s e g 94 s e g 93 s e g 92 s e g 91 s e g 90 s e g 89 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 seg output normal direction reverse direction line address d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 0 0 d0 com64 com64 page 8 d1 d2 d3 40h 41h 42h 43h com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 display start line does not access 65th, 66th, 67th, 68th line com64 com64 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 normal direction reverse direction com output com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 iconmode="1" iconmode="0" 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh line address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 40h 41h 42h 43h start partial display area (8+1) image location (1l[2:0]) + partial display area width (11 hex ) <= multiplexing rate (40 hex ) il[2:0] il[2:0] start partial display area (9)
STE2007 display data ram (ddram) 39/62 5.4 command parameters default configuration table 17. command parameters default configuration status after power on after hw reset after sw reset description driver status mcu txdata?mode mcu txdata?mode mcu txdata?mode power saver mode power saver mode power saver mode power saver mode display mode all pixel on all pixel on all pixel on inversion off off off display off off off frame memory random no change no change page address 0hex 0hex 0hex columns address 0hex 0hex 0hex display start line 0hex 0hex 0hex segment drivers direction normal normal normal common drivers direction normal normal normal vor - voltage range 4hex 4hex 4hex electronic volume 90hex 90hex 90hex power control register booster off booster off booster off id byte 0hex 0hex 0hex ida/idb pads charge pump 5x 5x 5x bias ratio 1/10 1/10 1/10 vlcd temperature comp. 0ppm 0ppm 0ppm n-line inversion frame inv. frame inv. frame inv. multiplexing rate 1/68 1/68 1/68 refresh rate 80hz 80hz 80hz image location 0hex 0hex 0hex icon mode disabled disabled disabled
instruction setups STE2007 40/62 6 instruction setups 6.1 initialization (power on sequence) 6.2 display data writing sequence 6.3 power off v0-voltage range (**h) electronic volume (**h) power saver off (display all points off (a4h)) power control set (2fh) reset status power on page address set (b*h) column address set upper 3-bit address (1*h) column address set lower 4-bit address (0*h) display data write display on (afh) this command is need- ed only at 1st time after initialization. optional status vdd - gnd power off vddi - gnd power off min.20ms power saver status or booster off status !res pin="low level" vdd - gnd power off vddi - gnd power off min. 0ms !res pin="low level"
STE2007 power on/power off timing sequence 41/62 7 power on/power off timing sequence figure 34 shows the timing diagram for power on/power down sequences. figure 34. timing for phone?s power on sequence when vdd,vddcp up before vddi xcs,sdain,xres can become ?high? simultaneously with vddi (tcs>0,tpi>0;tp2>0). trs= max 5000ns (internal reset time- see ac characteristics paragraph) t pwroff1 >0ms must be considered when driver is in power saver or booster off status t pwroff2 >20ms must be considered when driver is in normal working condition vddi, vdd and vdd_cp can come up/go down in any sequence vddi can be up with vdd, vddcp down and viceversa. if only one supply rail is up, the driver is forced in reset state. if vdd is high after vddi all timing referred to vddi must be referred to vdd (fig. 24) figure 35. timing for phone?s power on sequence when vddi up before vdd vddi vdd !res internal reset tp2 >0 s tp1 > 0 trs = max. 5 s reset state reset state !cs trs = max. 5 s t pwroff1 >0 ms t pwroff2 >20ms tp1 > 0 tcs >0 s inputs tpi >0 s tpi >0 s outputs high-z high-z tcs >0 s vddi vdd !res internal reset tp2 >0 s tp1 < 0 trs = max. 5 s reset state reset state !cs trs = max. 5 s t pwroff1 >0 ms t pwroff2 >20ms tp1 < 0 tcs >0 s sdain tpi >0 s tpi >0 s sdaout high-z high-z tcs >0 s
power on/power off timing sequence STE2007 42/62 table 18. instruction set command code function (d/c)d7d6d5d4d3d2d1d0hex display on/off 0 1010111 0 1 ae af lcd display 0: off, 1: on display normal/reverse 0 1010011 0 1 a6 a7 lcd display 0: normal, 1: reverse display all points on/off 0 1010010 0 1 a4 a5 lcd display 0: normal display, 1: all points on page address set 0 1 0 1 1 address sets the ddram page address column address set upper 3?bit address 0 0 0 0 1 * address sets the ddram column address column address set lower 4?bit address 0 0 0 0 0 address display start line address set 001 address sets the ddram display start line address segment driver direction 0 1010000 0 1 a0 a1 sets the correspondence between the ddram column address and the seg driver output. 0:normal, 1: reverse common driver direction select 01100 0 1 *** sets the correspondence between the ddram line address and the com driver output. 0: normal, 1: reverse display data write 1 write data writes to the ddram self test/identification data reading 0 1 1 0 1 1 0 1 1 db identification byte power control set 0 00101 operating mode sets the on?chip power supply circuit operating mode vo-range 0 0 0 1 0 0 vo-range sets the electronic volume value electronic volume 0 1 0 0 electronic volume value sets the electronic volume value power saver ? ???????? compound command of display off and display-all-points-on reset 0 11100010e2internal reset nop 0 1 1 1 0 0 0 1 1 e3 non?operation vop 0 11100001e1 sets the vlcd 0vop[7:0] termal compensation 0 0011100038 set vlcd slope in temperature 0 ***** thermal comp
STE2007 power on/power off timing sequence 43/62 * = disabled bits. command code function (d/c)d7d6d5d4d3d2d1d0hex charge pump 0 001111013d sets the charge pump mux factor 0 ****** charge pump refresh rate 0 11101111ef sets the display refresh frequency 0 ****** refersh rate bias ratio 0 0 0 1 1 0 bias ratio sets the vlcd n-line inversion 0 10101101ad 0 * * f1 n-line inversion number of lines 0 1 1 0 1 0 mux rate image location 0 10101100ac set initial row on display 0 * * * * * il[2:0] icon mode 0 1111100 ico n stm test mode1 0 10101001a9 reserved for stm (stm test mode) 0 ******** stm test mode2 0 1 0 1 0 1 0 1 0 aa reserved for stm (stm test mode) stm test mode3 0 1 0 1 0 1 0 1 1 ab reserved for stm (stm test mode) stm test mode4 0 1 0 1 0 1 0 0 0 a8 reserved for stm (stm test mode) stm test mode5 0 1 1 1 1 1 1 1 1 ff reserved for stm (stm test mode) stm test mode6 0 1 1 1 1 1 1 0 0 fc reserved for stm (stm test mode) stm test mode7 0 1 1 1 1 1 1 1 0 fe reserved for stm (stm test mode) stm test mode8 0 1 1 1 1 1 1 0 1 fd reserved for stm (stm test mode) table 18. instruction set (continued)
commands STE2007 44/62 8 commands 8.1 display on/off this command turns the display on and off table 19. display on/off when the display off command is executed in the display all points on mode, power saver mode is entered. see the section on the power saver for details. 8.2 display normal/reverse this command can reverse the lit and unlit without overwriting the contents of the ddram. table 20. display normal/reverse 8.3 display all points on/off this command makes it possible to force all display points on regardless of the content of the ddram. even when this is done, the ddram contents are maintained. this command takes priority over the display normal/reverse command. table 21. display all points on/off when the display all points on command is executed when in the display off mode, power saver mode is entered. see the section on the power saver for details. (d/c)d7d6d5d4d3d2d1d0hex setting 0 10101110ae display off 0 1 af display on (d/c)d7d6d5d4d3d2d1d0hex setting 0 10100110a6 normal:ddram data ?h?=lcd on voltage 01a7 reverse:ddram data ?l?=lcd on voltage (d/c)d7d6d5d4d3d2d1d0hex setting 0 10100100a4 normal display mode 0 1 a5 display all points on
STE2007 commands 45/62 8.4 page address set this command specifies the page address of the ddram. specifying the page address and column address enables to access a desired bit of the ddram. after the last column address (5fh), page address is incremented by +1. after the very last address (column = 5fh, page = 8h), page address return to 0h. table 22. page address set 8.5 column address set this command specifies the column address of the ddram. the column address is split into two sections (the upper 3?bits and lower 4?bits) when it is set. each time the ddram is accessed, the column address automatically increments by +1, imaging it possible for the mcu to continuously access to the display data. after the last column address (5fh), column address returns to 00h. table 23. column address set * disabled bit (d/c)d7d6d5d4d3d2d1d0hex setting 0 10110000b0 0h 00001b11h 00010b22h 0::: 01000b88h (d/c)d7d6d5d4d3d2d1d0 setting 0 0 0 0 1 * a6 a5 a4 upper bit address 0 a3 a2 a1 a0 lower bit address (d/c) a6a5a4a3a2a1a0 column address 0 0000000 00h 0 0000001 01h 0 0000010 02h .. .. 0 1011110 5eh 0 1011111 5fh
commands STE2007 46/62 8.6 display start line address set this command is used to specify the display start line address of the ddram. if the display start line address is changed dynamically using this command, then screen scrolling, page swapping can be performed. table 24. display start line address set display start line assress con be used in partial dispaly mode to relocate the partial display window on the screen. display start line + partial display area with must be smaller or equal to the number of line selected. 8.7 segment driver direction select this command can reverse the correspondence between the ddram column address and the segment driver output. table 25. segment driver direction select 8.8 common driver direction select this command can reverse the correspondence between the ddram line address and the common driver output. table 26. common driver direction select * disabled bit (d/c)d7d6d5d4d3d2d1d0hex setting 00100000040 0h 00100000141 1h 00100001042 2h :: : 0011111107e 3eh 0011111117f 3fh (d/c)d7d6d5d4d3d2d1d0hex setting 0 10100000a0 normal 01a1reverse (d/c)d7d6d5d4d3d2d1d0 setting 0 11000* * * normal 1*** reverse
STE2007 commands 47/62 8.9 display data write this command writes 8?bit data to the specified ddram address. since the column address is automatically incremented by +1 after each write, the mcu can continuously write multiple?word data. table 27. display data write 8.10 data reading from driver (driver txdata?mode) these commands set sdaout to driver txdata?mode and enable to read the identification byte. table 28. id byte 8.11 power control set this command sets the on?chip power supply function on/off. table 29. power control set (d/c) d7d6d5d4d3d2d1d0 1 write data (d/c)d7d6d5d4d3d2d1d0hex setting 0 11011011db reads id byte 0 0 0 idb ida 0 0 0 0 pad default (d/c)d7d6d5d4d3d2d1d0hex setting 00010100028 booster : off voltage regulator:off voltage follower : off 0 00129 0 0102a 0 0112b 0 1002c 0 1012d 0 1102e 0 1112f booster : on voltage regulator : on voltage follower : on
commands STE2007 48/62 8.12 vlcd set the lcd voltage vlcd at reference temperature (t a = 25c) can be set using the voltage range v0r, electronic volume ev and vop registers content according to the following formula: vlcd (t=t a ) = ( v0p[7:0] + ev[4:0] - 16 + 32 v0r[2:0]) b + vlcd min with the following values: for information on vlcd thermal compensation see par. 8.18 . figure 36. figure 37. 8.12.1 v0r - voltage range set this command sets a value of the voltage range. table 30. v0r ? voltage range symbol value unit note b 0.04 v single voltage step vlcd min 3v t a 25 c room temperature vout b vop[7:0]*b+v-or 00h ffh 10h 11h 12h 1fh 00h ev[3:0] 3v 13.20v ev[4:0] v0r[2:0] dac vout step: 40mv range 3v-13.20v thermal compensation (d/c)d7d6d5d4d3d2d1d0 setting 0 00100v0r - voltage rangecommand identifier + data field
STE2007 commands 49/62 table 31. v0r 8.12.2 vop set contrast setting adjustment . table 32. vop set table 33. vop (d/c)d7d6d5d4d3d2d1d0hex v0r value 32 v0r b + vlcd min 0 0010000020 0 3.00 v 0 00121 1 4.28 v 0 01022 2 5.56 v 0 01123 3 6.84 v 0 1 0 0 24 4 8.12 v (default) 0 10125 5 9.40 v 0 1 1 0 26 6 10.68 v 0 1 1 1 27 7 11.96 v (d/c)d7d6d5d4d3d2d1d0hex function 0 1 1 1 0 0 0 0 1 e1 command identifier 0 vop7vop6vop5vop4vop3vop2vop1vop0 data field vop7 vop6 vop5 vop4 vop3 vop2 vop1 vop0 hex vop adjustment 0000000000 0 step (default) 0000000101 +1 step 0000001002 +2 step ::::::::: : 011111117f +127 step 1000000080 0 step 1000000181 -1 step ::::::::: : 11111101fd -125 step 11111110fe -126 step 11111111ff -127 step
commands STE2007 50/62 8.12.3 electronic volume this command sets a value of electronic volume ev for the vlcd voltage regulator, to adjust the contrast of lcd panel display (end user). table 34. electronic volume table 35. ev 8.13 power saver mode if the display all points on command is executed when the display is in display off mode, power saver mode is entered. this mode stops every operation of the lcd display system. figure 38. power saver mode the internal states in power saver mode are as follows: ? the oscillation circuit is stopped ? the lcd power supply circuit is stopped ? the lcd driver circuit is stopped and segment/common driver outputs to the vss level ? the display data and operation mode before execution of the power saver are held, and the mcu can access to the ddram and internal registers. (d/c)d7d6d5d4d3d2d1d0 setting 0 1 0 0 electronic volume value command identifier + data field (d/c)d7d6d5d4d3d2d1d0hex ev value vlcd voltage 01000000080 0 step low 0 0 0 0 0 1 81 1 step 0 0 0 0 1 0 82 2 step ::::: 0 1 0 0 0 0 90 16 step (default) ::::: 0 1 1 1 1 0 9e 30 step 0 1 1 1 1 1 9f 31 step high power saver (display off & display all points on power saver mode powersaver off (display all points off) power saver mode canceled command effect
STE2007 commands 51/62 8.14 reset when this command is issued, the driver is initialized.this command doesn?t change ddram content. table 36. reset 8.15 nop non?operation command. table 37. nop 8.16 image location image location command table 38. image location table 39. image location (d/c) d7 d6 d5 d4 d3 d2 d1 d0 hex function 0 11100010e2 command identifier (d/c) d7 d6 d5 d4 d3 d2 d1 d0 hex function 0 11100011e3 command identifier (d/c) d7 d6 d5 d4 d3 d2 d1 d0 hex function 0 10101100ac command identifier 0 *****il2il1il0 data field il2 il1 il0 function 0 0 0 0 lines 0 0 1 8 lines 0 1 0 16 lines 0 1 1 24 lines 1 0 0 32 lines 1 0 1 48 lines 1 1 0 56 lines 1 1 1 64 lines
commands STE2007 52/62 8.17 bias ratio it is possible to select different bias ratio. table 40. bias ratio table 41. bias ratio figure 39. bias levels generator (d/c) d7d6d5d4d3d2d1d0 function 0 0 0 1 1 0 br2 br1 br0 command identifier + data field br2 br1 br0 function 0 0 0 bias ratio =1/10 - 81 lines 0 0 1 bias ratio = 1/9 - 65 lines 0 1 0 bias ratio =1/8 - 49 lines 0 1 1 bias ratio = 1/7 - 33 lines 1 0 0 bias ratio =1/6 - 25 lines 1 0 1 bias ratio = 1/5 - 17 lines 1 1 0 bias ratio =1/4 - 9 lines 1 1 1 not used r v lcd v ss v lcd v lcd v lcd v lcd 9 10 r 6 r r r 8 10 2 10 1 10 r v lcd v ss v lcd v lcd v lcd v lcd 8 9 r 5 r r r 7 9 2 9 1 9 br=000 br=001 r v lcd v ss v lcd v lcd v lcd v lcd 7 8 r 4 r r r 6 8 2 8 1 8 r v lcd v ss v lcd v lcd v lcd v lcd 6 7 r 3 r r r 5 7 2 7 1 7 br=010 br=011 r v lcd v ss v lcd v lcd v lcd v lcd 5 6 r 2 r r r 4 6 2 6 1 6 r v lcd v ss v lcd v lcd v lcd v lcd 4 5 r 1 r r r 3 5 2 5 1 5 br=100 br=101 r v lcd v ss v lcd v lcd v lcd v lcd 3 4 r 4 r r r 2 4 2 4 1 4 br=110
STE2007 commands 53/62 8.18 temperature compensation its is possible to select different vlcd temperature compensation coefficients. table 42. vlcd temperature compensation temperature compensation formula: vlcd(t) = vlcd(t a ) [1 + (t(c) - t a ) tc] tc = temperature compensation coefficients t(c) = temperature vlcd(t a ) = lcd voltage at t a temperature (room temperature) table 43. tc 8.19 charge pump multiplication factor it is possible to select different charge pump multiplication factors. table 44. charge pump setting (d/c)d7d6d5d4d3d2d1d0hex function 0 0011100038 command identifier 0 ***** thermal compensation tc data field tc2 tc1 tc0 tc value 000 tc= 0 ppm 001 tc= -300 ppm 010 tc= -600 ppm 011 tc= -900 ppm 100 tc= -1070 ppm 101 tc= -1200 ppm 110 tc= -1500 ppm 111 tc= -1800 ppm (d/c) d7 d6 d5 d4 d3 d2 d1 d0 hex function 0 0 0 1 1 1 1 0 1 3d command identifier 0 ******cp1cp0 data field
commands STE2007 54/62 table 45. charge pump multiplication factor 8.20 refresh rate it is possible to select different refresh rate. table 46. refresh rate setting table 47. refresh rate 8.21 icon mode icon mode ? 0: icon mode disabled ? 1: icon mode enabled table 48. icon mode 8.22 n- line inversion n-line inversion function. table 49. n-line inversion cp1 cp0 function 00 5 x 01 4 x 10 3 x 1 1 not used (d/c) d7 d6 d5 d4 d3 d2 d1 d0 hex function 0 11101111ef command identifier 0 * * * * * * rr1 rr0 data field rr1 rr0 function 00 80 hz 01 75 hz 10 70 hz 1 1 65 hz (d/c) d7d6d5d4d3d2d1d0 function 0 1 1 1 1 1 0 0 icon command identifier (d/c) d7 d6 d5 d4 d3 d2 d1 d0 hex function 0 10101101ad command identifier 0 * * f1 nl4 nl3 nl2 nl1 nl0 data field
STE2007 pad coordinates 55/62 the xor function defines the polarity as the result of the logical xor between the n-line and the frame polarity. 8.23 number of lines multiplexing rate setting command. table 51. number of lines table 52. multiplexing rate 9 pad coordinates see table 53: pad coordinates and table 55: alignment marks coordinates . table 50. n-line f1 nl4 nl3 nl2 nl1 nl0 function n row *00000 n-line inversion disabled (default) 0***** xor function disabled 1***** xor function enabled *00001 n-line inversion enabled 2 *00010 n-line inversion enabled 3 :::::: : : *11111 n-line inversion enabled 32 (d/c) d7d6d5d4d3d2d1d0 function 0 1 1 0 1 0 m2 m1 m0 command identifier + data field m2 m1 m0 function 0 0 0 68 lines (default) 0 0 1 65 lines 0 1 0 49 lines 0 1 1 33 lines 1 0 0 33 lines partial display 1 0 1 25 lines partial display 1 1 0 17 lines partial display 1 1 1 9 lines partial display
pad coordinates STE2007 56/62 table 53. pad coordinates name pad x ( m) y( m) name pad x ( m) y( m) r16 1 -2632.5 -514.35 c25 35 -1102.5 -514.35 r14 2 -2587.5 -514.35 c26 36 -1057.5 -514.35 r12 3 -2542.5 -514.35 c27 37 -1012.5 -514.35 r10 4 -2497.5 -514.35 c28 38 -967.5 -514.35 r8 5 -2452.5 -514.35 c29 39 -922.5 -514.35 r6 6 -2407.5 -514.35 c30 40 -877.5 -514.35 r4 7 -2362.5 -514.35 c31 41 -832.5 -514.35 r2 8 -2317.5 -514.35 c32 42 -787.5 -514.35 r0 9 -2272.5 -514.35 c33 43 -742.5 -514.35 c0 10 -2227.5 -514.35 c34 44 -697.5 -514.35 c1 11 -2182.5 -514.35 c35 45 -652.5 -514.35 c2 12 -2137.5 -514.35 c36 46 -607.5 -514.35 c3 13 -2092.5 -514.35 c37 47 -562.5 -514.35 c4 14 -2047.5 -514.35 c38 48 -517.5 -514.35 c5 15 -2002.5 -514.35 c39 49 -472.5 -514.35 c6 16 -1957.5 -514.35 c40 50 -427.5 -514.35 c7 17 -1912.5 -514.35 c41 51 -382.5 -514.35 c8 18 -1867.5 -514.35 c42 52 -337.5 -514.35 c9 19 -1822.5 -514.35 c43 53 -292.5 -514.35 c10 20 -1777.5 -514.35 c44 54 -247.5 -514.35 c11 21 -1732.5 -514.35 c45 55 -202.5 -514.35 c12 22 -1687.5 -514.35 c46 56 -157.5 -514.35 c13 23 -1642.5 -514.35 c47 57 -112.5 -514.35 c14 24 -1597.5 -514.35 c48 58 112.5 -514.35 c15 25 -1552.5 -514.35 c49 59 157.5 -514.35 c16 26 -1507.5 -514.35 c50 60 202.5 -514.35 c17 27 -1462.5 -514.35 c51 61 247.5 -514.35 c18 28 -1417.5 -514.35 c52 62 292.5 -514.35 c19 29 -1372.5 -514.35 c53 63 337.5 -514.35 c20 30 -1327.5 -514.35 c54 64 382.5 -514.35 c21 31 -1282.5 -514.35 c55 65 427.5 -514.35 c22 32 -1237.5 -514.35 c56 66 472.5 -514.35 c23 33 -1192.5 -514.35 c57 67 517.5 -514.35 c24 34 -1147.5 -514.35 c58 68 562.5 -514.35
STE2007 pad coordinates 57/62 c59 69 607.5 -514.35 c94 104 2182.5 -514.35 c60 70 652.5 -514.35 c95 105 2227.5 -514.35 c61 71 697.5 -514.35 r1 106 2272.5 -514.35 c62 72 742.5 -514.35 r3 107 2317.5 -514.35 c63 73 787.5 -514.35 r5 108 2362.5 -514.35 c64 74 832.5 -514.35 r7 109 2407.5 -514.35 c65 75 877.5 -514.35 r9 110 2452.4 -514.35 c66 76 922.5 -514.35 r11 111 2497.5 -514.35 c67 77 967.5 -514.35 r13 112 2542.5 -514.35 c68 78 1012.5 -514.35 r15 113 2587.5 -514.35 c69 79 1057.5 -514.35 r17 114 2632.5 -514.35 c70 80 1102.5 -514.35 r19 115 2831.85 -450.0 c71 81 1147.5 -514.35 r21 116 2831.85 -405.0 c72 82 1192.5 -514.35 r23 117 2831.85 -360.0 c73 83 1237.5 -514.35 r25 118 2831.85 -315.0 c74 84 1282.5 -514.35 r27 119 2831.85 -270.0 c75 85 1327.5 -514.35 r29 120 2831.85 -225.0 c76 86 1372.5 -514.35 r31 121 2831.85 -180.0 c77 87 1417.5 -514.35 r33 122 2831.85 -135.0 c78 88 1462.5 -514.35 r35 123 2831.85 -90.0 c79 89 1507.5 -514.35 r37 124 2831.85 -45.0 c80 90 1552.5 -514.35 r39 125 2831.85 0.0 c81 91 1597.5 -514.35 r41 126 2831.85 45.0 c82 92 1642.5 -514.35 r43 127 2831.85 90.0 c83 93 1687.5 -514.35 r45 128 2831.85 135.0 c84 94 1732.5 -514.35 r47 129 2831.85 180.0 c85 95 1777.5 -514.35 r49 130 2831.85 225.0 c86 96 1822.5 -514.35 r51 131 2831.85 270.0 c87 97 1867.5 -514.35 r53 132 2831.85 315.0 c88 98 1912.5 -514.35 r55 133 2831.85 360.0 c89 99 1957.5 -514.35 r57 134 2831.85 405.0 c90 100 2002.5 -514.35 r59 135 2831.85 450.0 c91 101 2047.5 -514.35 r61 136 2632.5 514.35 c92 102 2092.5 -514.35 r63 137 2587.5 514.35 c93 103 2137.5 -514.35 r65 138 2542.0 514.35 table 53. pad coordinates (continued) name pad x ( m) y( m) name pad x ( m) y( m)
pad coordinates STE2007 58/62 r67 139 2497.5 514.35 vddi 174 -720.0 517.5 test3 140 2376.0 517.5 vddi 175 -792.0 517.5 test4 141 2304.0 517.5 vddi 176 -864.0 517.5 vss_aux 142 1944.0 517.5 vddi 177 -936.0 517.5 vss_aux 143 1872.0 517.5 vddi 178 -1008.0 517.5 vss_aux 144 1800.0 517.5 vddi 179 -1080.0 517.5 vss_aux 145 1728.0 517.5 vdd 180 -1224.0 517.5 n_res 146 1584.0 517.5 vdd 181 -1296.0 517.5 n_cs 147 1512.0 517.5 vdd 182 -1368.0 517.5 t2 148 1368.0 517.5 vdd 183 -1440.0 517.5 t1 149 1296.0 517.5 vdd 184 -1512.0 517.5 t0 150 1224.0 517.5 vdd 185 -1584.0 517.5 vss 151 1152.0 517.5 vdd_cp 186 -1656.0 517.5 vss 152 1080.0 517.5 vdd_cp 187 -1728.0 517.5 vss 153 1008.0 517.5 vlcd_sns 188 -1872.0 517.5 vss_lcd 154 936.0 517.5 vlcd 189 -1944.0 517.5 vss_lcd 155 864.0 517.5 vlcd 190 -2016.0 517.5 vss_lcd 156 792.0 517.5 vlcd 191 -2088.0 517.5 vss_cp 157 720.0 517.5 vlcd 192 -2160.0 517.5 vss_cp 158 648.0 517.5 test4 193 -2304.0 517.5 vss_cp 159 576.0 517.5 test5 194 -2376.0 517.5 dc 160 432.0 517.5 r66 195 -2497.5 514.35 sdaout 161 360.0 517.5 r64 196 -2542.5 514.35 sdin 162 288.0 517.5 r62 197 -2587.5 514.35 sdout 163 216.0 517.5 r60 198 -2632.5 514.35 sclk 164 144.0 517.5 r58 199 -2831.85 450.0 vref_buff 165 72.0 517.5 r56 200 -2831.85 405.0 vss_aux 166 -72.0 517.5 r54 201 -2831.85 360.0 sel1 167 -144.0 517.5 r52 202 -2831.85 315.0 sel0 168 -216.0 517.5 r50 203 -2831.85 270.0 sa1 169 -288.0 517.5 r48 204 -2831.85 225.0 sa0 170 -360.0 517.5 r46 205 -2831.85 180.0 idb 171 -432.0 517.5 r44 206 -2831.85 135.0 ida 172 -504.0 517.5 r42 207 -2831.85 90.0 osc_in 173 -576.0 517.5 r40 208 -2831.85 45.0 table 53. pad coordinates (continued) name pad x ( m) y( m) name pad x ( m) y( m)
STE2007 pad coordinates 59/62 r38 209 -2831.85 0.0 r26 215 -2831.85 -270.0 r36 210 -2831.85 -45.0 r24 216 -2831.85 -315.0 r34 211 -2831.85 -90.0 r22 217 -2831.85 -360.0 r32 212 -2831.85 -135.0 r20 218 -2831.85 -405.0 r30 213 -2831.85 -180.0 r18 219 -2831.85 -450.0 r28 214 -2831.85 -225.0 table 53. pad coordinates (continued) name pad x ( m) y( m) name pad x ( m) y( m)
chip mechanical drawing STE2007 60/62 10 chip mechanical drawing figure 40. alignment marks dimensions table 54. mechanical dimensions parameter dimensions wafer thickness 500 m die size (x x y) 5.92 mm x 1.29 mm bumps size on columns and segments side 28 m x 89 m x 15 pad size on columns and segments side 35 m x 96 m bumps pitch on columns and segments side 45 m bumps size on interfaces side 55 m x 73 m x 15 pad size on interfaces side 64 m x 82 m bumps pitch on interfaces side 72 m spacing between bumps 17 m table 55. alignment marks coordinates marks x y mark1 -2834.55 517.05 mark2 2834.55 517.05 mark3 -2834.55 -517.05 mark4 2834.55 -517.05 mark5 2205.0 517.05 85 m 35 m
STE2007 ordering information 61/62 11 ordering information 12 revision history table 56. order codes part number type STE2007die2 bumped dice on waffle pack table 57. document revision history date revision changes 09-nov-2005 1 initial release. 13-mar-2006 2 adjustments in abs max ratings regarding esd in ta b l e 7 . adjustments on dc & ac charactersitics (v lcd , i(v ddi ) in ta bl e 8 & f frame in ta b l e 9 ) 12-dec-2006 3 reviewed operating temperature range in chapter 3: electrical characteristics .
STE2007 62/62 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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